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Title: | High throughput and high capacity asynchronous pipeline using hybrid logic |
Authors: | Sravani, K. Rao, R. |
Issue Date: | 2017 |
Citation: | Proceedings of 2017 International Conference on Innovations in Electronics, Signal Processing and Communication, IESC 2017, 2017, Vol., , pp.11-15 |
Abstract: | This paper proposes a novel high throughput and high capacity asynchronous pipeline architecture, named High capacity Hybrid logic pipeline. The proposed pipeline architecture is intended for the data paths that use domino logic. This pipeline structure, combines the merits of hybrid logic encoding scheme(robustness and simplicity) and High capacity single-rail protocol (high throughput and full buffering capacity). The validity of the proposed pipeline structure has been tested by simulating a 4-bit, 10-stage FIFO in 180 nm technology. The FIFO has exhibited a throughput of 2.23 giga-items/s and this number is 23.2% higher than one of the best existing pipeline (High capacity single-rail). � 2017 IEEE. |
URI: | http://idr.nitk.ac.in/jspui/handle/123456789/8198 |
Appears in Collections: | 2. Conference Papers |
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