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DC Field | Value | Language |
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dc.contributor.author | Sharma, B.S. | |
dc.contributor.author | Bhat, M.S. | |
dc.date.accessioned | 2020-03-30T10:02:37Z | - |
dc.date.available | 2020-03-30T10:02:37Z | - |
dc.date.issued | 2017 | |
dc.identifier.citation | 2017 IEEE 8th Annual Ubiquitous Computing, Electronics and Mobile Communication Conference, UEMCON 2017, 2017, Vol.2018-January, , pp.271-277 | en_US |
dc.identifier.uri | http://idr.nitk.ac.in/jspui/handle/123456789/7667 | - |
dc.description.abstract | Structures based on Indium Gallium Arsenide (InGaAs) have attracted a lot of attention in Metal Oxide Semiconductor Field Effect Transistor (MOSFET) technology, recently. In this paper, we investigate the performance of a nano scale dual-gate MOSFET using InGaAs, and propose the design of a high performance In0.55Ga0.45As transistor with modified substrate geometry. Impact of changing the mole-fraction 'x' in In1-xGaxAs on the device performance is observed. To achieve best performance, the device geometry, relative mole fraction of In & Ga, the doping concentration of source/drain region and channel stop implant are varied. Simulations are performed to obtain output and transfer characteristics considering a N+ poly gate as well as a metallic (Al) gate for the proposed device. Simulations show excellent subthreshold slope (~ 62mV/dec), DIBL (~ 30 m V/V) and ION/IOFF = 2.23 � 106 values. As an application, an inverter is designed using this device and its DC and Transient responses for resistive and saturated enhancement NMOS load are plotted. � 2017 IEEE. | en_US |
dc.title | Design of high performance dual-gate nano-scale In0.55Ga0.45 as transistor with modified substrate geometry | en_US |
dc.type | Book chapter | en_US |
Appears in Collections: | 2. Conference Papers |
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