Design of CMOS RF receiver front-end for IEEE 802.11b

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DC Field	Value	Language
dc.contributor.author	Konidala, N.
dc.contributor.author	Bhat, M.S.
dc.date.accessioned	2020-03-30T10:02:37Z	-
dc.date.available	2020-03-30T10:02:37Z	-
dc.date.issued	2008
dc.identifier.citation	2008 International Conference on Electronic Design, ICED 2008, 2008, Vol., , pp.-	en_US
dc.identifier.uri	http://idr.nitk.ac.in/jspui/handle/123456789/7664	-
dc.description.abstract	This paper presents the design of a fully integrated receiver front-end for a 2.4GHz RF transceiver. The proposed receiver front end (Low-Noise Amplifier and Mixer) is based on a direct conversion architecture designed in 0.18?m CMOS technology. The chip provides a down conversion gain to the 50 MHz IF of 13.2 dB, SSB Noise Figure (NF) of 7.65 dB and a 3rd-order input intercept point (IIP3) of -14.6dBm consuming 50.6mW at1.8 V. �2008 IEEE.	en_US
dc.title	Design of CMOS RF receiver front-end for IEEE 802.11b	en_US
dc.type	Book chapter	en_US
Appears in Collections:	2. Conference Papers

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