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| DC Field | Value | Language |
|---|---|---|
| dc.contributor.author | Bhai, S.P.M. | |
| dc.contributor.author | Gaonkar, D.N. | |
| dc.date.accessioned | 2020-03-30T10:02:37Z | - |
| dc.date.available | 2020-03-30T10:02:37Z | - |
| dc.date.issued | 2016 | |
| dc.identifier.citation | 2016 IEEE 1st International Conference on Control, Measurement and Instrumentation, CMI 2016, 2016, Vol., , pp.499-502 | en_US |
| dc.identifier.uri | http://idr.nitk.ac.in/jspui/handle/123456789/7663 | - |
| dc.description.abstract | In this paper, an Analog to Digital Converter (ADC) based on binary-search algorithm is proposed. Existing binary-search based ADC design requires 2N-1 comparators for an N-bit ADC while the proposed design requires only N comparators. This ADC uses a switching network made up of static logic gates and MOSFET switches for predicting the reference voltage for the comparators. The proof-of-concept 3-bit ADC only consists of a reference ladder, 3 comparators, 6 n-MOSFET switches and 6 logic gates. The proposed 3-bit prototype was simulated using TINA-TI simulation software. The functionality of the ADC was ensured by giving sine and ramp input to the ADC. Also, the settling time of the ADC for different input voltage ranges was found out by giving step input to the ADC. � 2016 IEEE. | en_US |
| dc.title | Design of binary search ADC using N comparators | en_US |
| dc.type | Book chapter | en_US |
| Appears in Collections: | 2. Conference Papers | |
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