Please use this identifier to cite or link to this item: https://idr.l2.nitk.ac.in/jspui/handle/123456789/7496
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dc.contributor.authorKumar, K.N.L.
dc.contributor.authorSrihari, P.
dc.contributor.authorSatapathi, G.S.
dc.contributor.authorSharma, G.V.K.
dc.date.accessioned2020-03-30T09:59:15Z-
dc.date.available2020-03-30T09:59:15Z-
dc.date.issued2017
dc.identifier.citation2017 IEEE Radar Conference, RadarConf 2017, 2017, Vol., , pp.1379-1382en_US
dc.identifier.urihttp://idr.nitk.ac.in/jspui/handle/123456789/7496-
dc.description.abstractThis paper proposes a novel high speed radar pulse compressor implementation for complementary sequences. The high speed implementation is accomplished by incorporating the retiming technique to reduce the critical path of the circuit. In addition, unfolding the retimed pulse compressor further increases the speed by parallel operation. This concept is implemented on field programmable gate array (FPGA) and the experimental results demonstrate that, three-retimed-unfolded circuit (J = 3) is 2.78 times faster than the original circuit. � 2017 IEEE.en_US
dc.titleA high speed complementary pulse compressor and its implementation of FPGAen_US
dc.typeBook chapteren_US
Appears in Collections:2. Conference Papers

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