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dc.contributor.authorHegde, K.V.-
dc.contributor.authorKulkarni, V.-
dc.contributor.authorHarshavardhan, R.-
dc.contributor.authorSumam, David S.-
dc.date.accessioned2020-03-30T09:58:38Z-
dc.date.available2020-03-30T09:58:38Z-
dc.date.issued2015-
dc.identifier.citationProceedings - 2015 IEEE 29th International Parallel and Distributed Processing Symposium Workshops, IPDPSW 2015, 2015, Vol., , pp.196-201en_US
dc.identifier.urihttps://idr.nitk.ac.in/jspui/handle/123456789/7205-
dc.description.abstractIn this paper, we propose an adaptive reconfigurable architecture for image denoising. First part of this paper outlines an efficient noise detection hardware for Gaussian & impulse noise detection and suitable filters for denoising. With a robust noise detection method including a novel Gaussian noise detection method, we also explore the dynamic detection of noise in an image giving adaptability to the architecture for a better quality of denoising. Proposed architecture includes a decision making unit to find out the presence of noise as well as type of the noise, based on which a suitable filter is employed during run-time. An onboard microprocessor controls the reconfiguration and dataflow. Proposed architecture is tested on Xilinx Virtex-6 FPGA with localized noise and mixed noise conditions and it gives superior performance compared to the standard filters used. High quality denoising is achieved with simple filters on a reconfigurable region utilizing smaller area and lesser hardware resources. � 2015 IEEE.en_US
dc.titleAdaptive Reconfigurable Architecture for Image Denoisingen_US
dc.typeBook chapteren_US
Appears in Collections:2. Conference Papers

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