Please use this identifier to cite or link to this item:
https://idr.l2.nitk.ac.in/jspui/handle/123456789/7161
Full metadata record
DC Field | Value | Language |
---|---|---|
dc.contributor.author | Aparna, T. | |
dc.contributor.author | Polineni, S. | |
dc.contributor.author | Bhat, M.S. | |
dc.date.accessioned | 2020-03-30T09:58:34Z | - |
dc.date.available | 2020-03-30T09:58:34Z | - |
dc.date.issued | 2019 | |
dc.identifier.citation | 2018 IEEE Distributed Computing, VLSI, Electrical Circuits and Robotics, DISCOVER 2018 - Proceedings, 2019, Vol., , pp.152-157 | en_US |
dc.identifier.uri | http://idr.nitk.ac.in/jspui/handle/123456789/7161 | - |
dc.description.abstract | The design and simulation of a low power, high gain three stage operational transconductance amplifier (OTA) is presented. This OTA has a DC gain of 73.5 dB, a unity gain bandwidth (UGB) of 39.8 MHz and a phase margin of 59�. The total power consumed by OTA is 332 ?W. The DC gain and the power dissipation parameters of the OTA are found to be better than the previously published results of [1]-[4]. Further, a first order Delta Sigma Modulator (DSM) is designed as a vehicle to test the OTA by integrating it with a comparator and a DAC for a signal bandwidth of 2 kHz with an oversampling ratio (OSR) of 250 for low frequency biomedical applications. All the blocks are designed using UMC 180nm CMOS 1P9M technology, with 1.8 V supply voltage. The simulation results show that the in-band signal to noise and distortion ratio (SNDR) of the DSM is 53 dB, which is equivalent to 8.5 effective number of bits (ENOB). � 2018 IEEE. | en_US |
dc.title | A Three-Stage Operational Transconductance Amplifier for Delta Sigma Modulator | en_US |
dc.type | Book chapter | en_US |
Appears in Collections: | 2. Conference Papers |
Files in This Item:
There are no files associated with this item.
Items in DSpace are protected by copyright, with all rights reserved, unless otherwise indicated.