Please use this identifier to cite or link to this item: https://idr.l2.nitk.ac.in/jspui/handle/123456789/16303
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dc.contributor.authorGorre P.
dc.contributor.authorVignesh R.
dc.contributor.authorSong H.
dc.contributor.authorKumar S.
dc.date.accessioned2021-05-05T10:30:09Z-
dc.date.available2021-05-05T10:30:09Z-
dc.date.issued2021
dc.identifier.citationJournal of Infrared, Millimeter, and Terahertz Waves , Vol. 42 , 3 , p. 239 - 259en_US
dc.identifier.urihttps://doi.org/10.1007/s10762-021-00771-0
dc.identifier.urihttp://idr.nitk.ac.in/jspui/handle/123456789/16303-
dc.description.abstractThis work reports in first time a 100-Gb/s, ultra-low noise, variable gain multi-stagger tuned transimpedance amplifier (VGMST-TIA) over the D-band performance. The whole work is binding into two phases. The first phase involves the modeling and characterization of graphene field-effect transistor (GFET) with an optimized transition frequency of operation. While in the second phase, a TIA design employs a T-shaped symmetrical L-R network at the input, which mitigates the effect of photo diode capacitance and achieves a D-band of operation. The proposed work uses a VGMST to establish TIA, which realizes optimum noise performance. The high gain 3-stage VGMST-TIA effectively minimizes the white noise and illustrates a sharp out-of-band roll-off to achieve considerable noise reduction at high frequencies. The active feedback mechanism controls the transimpedance gain by tuning the control voltage which results better group delay. Besides, an L-C circuit is employed at the output to enhance bandwidth. The full TIA is implemented and fabricated using a commercial nano-manufacturing 9-nm graphene film FET on a silicon wafer using 0.065-μm process. The TIA achieves a flat transimpedance gain of 61.2 dBΩ with ± 9 ps group delay variation over the entire bandwidth. The proposed TIA measured an impedance bandwidth of 0.2 THz with ultra-low input-referred noise current density of 2.03 pA/√Hz. The TIA supports a 100-Gb/s data transmission due to large bandwidth; therefore, a bit-error-rate (BER) less than 10−12 is achieved. The chip occupies an area of 0.92 * 1.34 mm2 while consuming power of 21 mW under supply of 1.8 V. © 2021, The Author(s), under exclusive licence to Springer Science+Business Media, LLC part of Springer Nature.en_US
dc.titleA 61.2-dBΩ, 100 Gb/s Ultra-Low Noise Graphene TIA over D-Band Performance for 5G Optical Front-End Receiveren_US
dc.typeArticleen_US
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