Please use this identifier to cite or link to this item: https://idr.l2.nitk.ac.in/jspui/handle/123456789/14916
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dc.contributor.authorBhowmik B.
dc.contributor.authorBiswas S.
dc.contributor.authorDeka J.K.
dc.contributor.authorBhattacharya B.B.
dc.date.accessioned2021-05-05T10:15:59Z-
dc.date.available2021-05-05T10:15:59Z-
dc.date.issued2020
dc.identifier.citationProceedings of IEEE Computer Society Annual Symposium on VLSI, ISVLSI , Vol. 2020-July , , p. 200 - 205en_US
dc.identifier.urihttps://doi.org/10.1109/ISVLSI49217.2020.00044
dc.identifier.urihttp://idr.nitk.ac.in/jspui/handle/123456789/14916-
dc.description.abstractNetworks-on-chip (NoCs) provide the essential communication infrastructure for building today's on-chip multiprocessors. Albeit mesh is commonly used as the underlying interconnection architecture, other regular topologies such as octagons or spidergons, find recent applications to hybrid, small-world, and smart networks. Aggressive technology scaling, however, makes NoCs susceptible to manufacturing defects and causes failures in their operations. This paper presents a distributed, on-line built-in-self-test (BIST) mechanism that targets open faults on communication channels in an octagon NoC. We introduce a novel test scheduling scheme that exploits the knowledge of multithreading for reducing the overall test time with minimal degradation of performance. We evaluate the proposed test scheme for a 16-bit octagon NoC and report experimental results. © 2020 IEEE.en_US
dc.titleLocating open-channels in octagon networks on chip-microprocessorsen_US
dc.typeConference Paperen_US
Appears in Collections:2. Conference Papers

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