Please use this identifier to cite or link to this item: https://idr.l2.nitk.ac.in/jspui/handle/123456789/14776
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dc.contributor.authorHanumantha Rao G.
dc.contributor.authorMuhammed Mansoor C.B.
dc.contributor.authorRekha S.
dc.date.accessioned2021-05-05T10:15:46Z-
dc.date.available2021-05-05T10:15:46Z-
dc.date.issued2019
dc.identifier.citation2019 Global Conference for Advancement in Technology, GCAT 2019 , Vol. , , p. -en_US
dc.identifier.urihttps://doi.org/10.1109/GCAT47503.2019.8978311
dc.identifier.urihttp://idr.nitk.ac.in/jspui/handle/123456789/14776-
dc.description.abstractThis paper presents a low voltage, low power Proportional to Absolute Temperature (PTAT) current reference circuit with improved supply voltage sensitivity. The proposed circuit is designed and laid out in UMC 65 nm CMOS technology and simulated using Cadence Virtuoso. It generates a reference current (Iref) of 5 nA at 0.8 V supply voltage (Vdd) at room temperature (27°C). Composite transistors are used to improve the supply voltage sensitivity when compared to a traditional beta-multiplier circuit. The current reference circuit consumes a power of 8 nW and follows PTAT characteristics in the temperature range of 0°C to 80°C. The supply voltage sensitivity of Iref is 2.6 %/V, which shows that the proposed circuit is less sensitive to supply voltage variations. © 2019 IEEE.en_US
dc.titleA 0.8 V, 5 nA PTAT current reference circuit with improved supply voltage sensitivityen_US
dc.typeConference Paperen_US
Appears in Collections:2. Conference Papers

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