Design of High Resolution Delta Sigma Modulator in 180 nm CMOS technology

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DC Field	Value	Language
dc.contributor.author	Bonthala S.
dc.contributor.author	Uppoor Y.
dc.contributor.author	Nayak A.
dc.contributor.author	Polineni S.
dc.contributor.author	Bhat M.S.
dc.date.accessioned	2021-05-05T10:15:41Z	-
dc.date.available	2021-05-05T10:15:41Z	-
dc.date.issued	2019
dc.identifier.citation	Proceedings of the 2019 International Symposium on Embedded Computing and System Design, ISED 2019 , Vol. , , p. 78 - 83	en_US
dc.identifier.uri	https://doi.org/10.1109/ISED48680.2019.9096220
dc.identifier.uri	http://idr.nitk.ac.in/jspui/handle/123456789/14719	-
dc.description.abstract	This paper presents the design and simulation of a Delta Sigma Modulator (DSM) to be employed in a Delta Sigma Analog to Digital Converter. The designed modulator block comprises of a high gain Operational Transconductance Amplifier (OTA) of the folded cascode type providing a DC gain of 91dB and phase margin of 60° which is better than previously published results [3], [8], [5] in the similar domain. Signal to Quantization Noise ratio of 79.96 dB is obtained corresponding to an effective number of bits of 13 for a signal bandwidth of 2kHz and an oversampling ratio (OSR) of 1000, which is suitable for low frequency applications. All the necessary blocks are designed using UMC 180nm CMOS 1P9M technology with supply voltage of 1.8 V. © 2019 IEEE.	en_US
dc.title	Design of High Resolution Delta Sigma Modulator in 180 nm CMOS technology	en_US
dc.type	Conference Paper	en_US
Appears in Collections:	2. Conference Papers

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