Please use this identifier to cite or link to this item: https://idr.l2.nitk.ac.in/jspui/handle/123456789/14649
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dc.contributor.authorBhat K.G.
dc.contributor.authorLaxminidhi T.
dc.contributor.authorBhat M.S.
dc.date.accessioned2021-05-05T10:11:46Z-
dc.date.available2021-05-05T10:11:46Z-
dc.date.issued2020
dc.identifier.citationSadhana - Academy Proceedings in Engineering Sciences , Vol. 45 , 1 , p. -en_US
dc.identifier.urihttps://doi.org/10.1007/s12046-020-01421-2
dc.identifier.urihttp://idr.nitk.ac.in/jspui/handle/123456789/14649-
dc.description.abstractA resolution-independent successive approximation register (SAR) analog to digital converter (ADC) architecture based on a switched capacitor integrator is presented. Digital to analog converter (DAC) architecture uses charge sharing and integration principle for reference generation, using only six unit capacitors for a fully differential version. A 10-bit, 1.8-V and 0.9-MS/s SAR ADC is designed in 180-nm CMOS process. ADC architecture is area efficient when compared with SAR ADC with a binary weighted capacitor array DAC. The architecture is largely parasitic insensitive, also programmable resolution is possible with no hardware overhead. © 2020, Indian Academy of Sciences.en_US
dc.titleResolution-independent fully differential SCI-based SAR ADC architecture using six unit capacitorsen_US
dc.typeLetteren_US
Appears in Collections:5. Miscellaneous Publications

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